To facilitate data transfer at high frequency (e.g., greater than 500 Megabits per second (Mbps)) between integrated circuits (ICs) of silicon dies in a package, while each die in the package may be on a different process technology node and/or different operation power supply voltage, data sampling and clock synchronization between the dies can be very challenging. Furthermore, on-die systematic and random variations within each die, and also between dies, further exacerbate timing margin constrains. Without proper mitigations, the on-die systematic and random variations within each die, and also between dies, introduces design complexity, degrades link data transfer rate and compromises the overall system performance, which leads to functional failures in dies.